April 18–19, 2018 Boston Convention & Exhibition Center Boston, MA

ESC Boston 2018 Schedule Viewer

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Synchronous to Asynchronous Digital Design Flow to Halve Processing Power


William Ellersick (Founder and CEO, Analog Circuit Works)

Location: ESC Engineering Theater

Date: Thursday, April 19

Time: 3:00pm - 3:45pm

Pass type: Conference (Paid), Expo (Free) - Get your pass now!

Free Content & Activities: N/A

Conference Track: Embedded Hardware Design & Verification, Advanced Technologies

Vault Recording: TBD

Audience Level: N/A

Traditional synchronous design must incorporate timing margins to ensure correct operation under worst-case
delay conditions. However, the ongoing increase in process variation compounded with aging effects is causing
progressively larger delay variations, requiring more substantial timing margins and reducing the performance and
energy efficiency of traditional designs. We present a tool flow that reduces digital processing power by two to three times. The
flow converts traditional synchronous RTL to asynchronous logic, eliminating clocks and the need for timing
margins. The asynchronous logic can thus be run at lower voltage to achieve comparable performance, and clock
trees need not be driven, significantly improving power efficiency. Automated scripts are described that replace flip-flops
with latches, and insert delay lines along with simple asynchronous control logic to ensure correct operation.
Fully integrated DC to DC converters allow multiple supply voltages to independently optimize the power efficiency
of processors, logic, memory, and interface circuitry. The Virtuoso tool flow is used, from transistor level design and
simulation for integrated power management and interface circuitry, through synthesis, optimization, and
place/route. Case studies on digital circuitry in 250nm, 130nm, 28nm, and 22nm processes will be presented.


Digital processing power can be halved with an automated design and synthesis flow. Integrated DC to DC
converters can independently optimize the power efficiency of different circuit blocks. Consistent results have been
achieved across a wide range of process nodes and circuit types.