April 18–19, 2018Boston Convention & Exhibition CenterBoston, MA

ESC Boston 2017 Schedule Viewer

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  • Native Floating Point Code Generation for FPGA/ASIC

    Location:  160C
    Format: 45-Minute Technical Session
    Conference Track: Embedded Software, Embedded Hardware
    Session Type: Conference (Paid)
    Pass type: Conference (Paid) - Get your pass now!
    Vault Recording: TBD

    HDL Coder Native Floating Point support helps generates synthesizable VHDL or Verilog directly from single-precision Simulink models without needing tedious fixed-point conversion that could take many months for reasonably complex models. Hardware design has traditionally required data types to be completely converted to fixed point in order to realize mathematical operations on FPGA/ASIC. But many applications contain calculations with high dynamic range, which requires very large fixed-point word sizes to accommodate the magnitude and precision. Some proprietary floating point IP libraries are available, but they are black box implementations specific to a given device vendor. HDL Coder Native Floating Point generates readable, traceable, and synthesizable RTL.

    The generated code is highly accurate as measured in terms of units in last place (ULP) error, and supports the full range of IEEE 754 features, including Inf, NaN, and denormals. In addition to being highly optimized mathematical implementations out of the box, the floating point operators are native to HDL Coder, they can take full advantage of model level optimizations such as resource sharing and pipelining, so the generated code is area- and latency-efficient relative to other vendor specific floating point solutions. And for fine-grained tuning you can mix fixed-point and floating point in the same design when accommodating area and latency constraints of certain designs.

    With support for over 130 supported Simulink blocks, HDL Coder's Native Floating Point is beginning to be quickly adopted for applications that require high dynamic range calculations commonly found in mathematic equations like flux equations, cumulative distributive functions and state space equations, especially in motor control applications.

    This talk elaborates on some of the trends in FPGAs and high dynamic range implementation choices and use of Model Based Design to address these problems with HDLCoder